This invention relates generally EDA (electronic design automation) tools that execute on a computer for designing and testing electronic devices. More particularly, this invention relates to a class of EDA tools know as DFT (design-for-test). DFT tools are used to enhance the testability of products manufactured from designs by adding test hardware such a logic gates and registers to the design. At the time of manufacture, test patterns are then applied to each enhanced product to detect possible faults, or defects, in the product that may have occurred during manufacture.
Through continual manufacturing advances, integrated circuits (ICs) are being produced today that combine features that previously required separate ICs. These complex ICs are referred to in the industry as a xe2x80x9csystems-on-a-chipxe2x80x9d (SOCs) because they contain as much hardware as was contained in a system of interconnected ICs several years ago.
In traditional IC design, most circuits are designed from scratch. Standard, reusable parts of the circuit are limited to basic logic gates that may be selected from standard-cell libraries. In a SOC design, by contrast, the IC is often made up of large, predefined and pre-verified building blocks and few IC-specific parts. These reusable building blocks are known in the industry as xe2x80x9ccoresxe2x80x9d or xe2x80x9cintellectual propertyxe2x80x9d that typically consist of a pre-designed and pre-verified silicon circuit block. The cores are provided by suppliers in the form of software (such as a source code file written in a hardware description language) to the SOC designer, who embeds them into a larger design using an EDA tool. Examples of cores includes date processors, adders, and media access controllers.
Making easily testable integrated circuits is an important part of the IC design process. EDA test tools exist for creating test patterns that test for possible faults within an IC manufactured according to a design. Even with such tools, however, creating such test patterns takes significant effort because of the large number of gates within many ICs. With SOC designs having a multiple of embedded cores, the effort is even greater because of the greater complexity of the IC.
Suppliers of cores often provide test patterns that are specific for their cores. These test patterns are useful where the core is fabricated in a simple IC because they can be readily applied to and observed from the core through the input-output (I/O) pins of the IC. The test patterns, however, are not as useful where the core is embedded within a SOC design and cannot be reached by simple application of the test patterns to pins of the SOC. In such circumstances, much work must often be done to generate new test patterns that take into account the interconnections of the core to the other hardware within the SOC.
An objective of the invention, therefore, is to provide a means and method for creating a testable circuit design that includes one or more embedded cores. Another objective is to provide a means and method for using pre-existing core test patterns for testing the cores embedded within a larger circuit design.
In accordance with the invention, a computer-implemented method for creating a testable circuit design that includes one or more embedded cores is shown and described. The method comprises identifying an embedded core within the circuit design; associating certain pins of the embedded core with pins of the circuit design; and inserting into the circuit design access circuitry coupling the certain connection pins of the embedded core to the associated pins of the circuit design.
The method may further include providing test vectors for the embedded core; and generating test vectors for the circuit design by mapping the core test vectors applicable to the certain pins of the embedded core to the associated pins of the circuit design.
These and other, more specific aspects of the invention are described and shown in a following illustrative embodiment.